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Reads transfer data from system memory to the FPGA. If you select At Endpoint address , you can type the starting write address in Endpoint memory the Endpoint address field. This is a pulse, not a level, signal. Endpoint L1 acceptable latency Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state. Unsupported Request error for non-posted TLP. Is your design an Endpoint or Root Port?

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Removed performance tables for legacy devices. For more information about the hard and soft reset controllers, refer to Reset.

Clarified that the only Jungo driver that Altera delivers with this reference design is an executable file configured for the specific reference design. Maximum caining 1 us. Indicates that there is an uncorrectable error correction coding ECC error in the internal RX buffer. For a detailed explanation of this example design, refer to the Testbench and Design Example altwra. During a single cycle, the IP core can consume either a single header credit or both a header and a data credit.


The parameter maximum payload size sets the read-only value of the Maximum Payload Size Supported field of the Device Capabilities register bits 2: The timing for these operations complies with the Avalon-MM protocol described in the Avalon Interface Specifications.

The theoretical maximum throughput is calculated using the following formula: Master data parity error. To maximize resources, do not specify a the maximum payload size that is greater than the system maximum payload size. Select this option for variations where the received requests and received completions are roughly equal. Enable local management interface LMI.

To respond to memory read requests To send error messages This signal is not asserted when an Application Layer credit is consumed. Read-only bits are not affected.

The parameter maximum payload size sets the read-only value of the Maximum Payload Size Supported field of the Device Capabilities register bits 2: Specifies the maximum number of lanes supported. In this case, bits[ Defining memory as prefetchable allows contiguous data to be fetched ahead. For Gen1 and Gen2 operation, Gen3 outputs can be left floating.


Getting the Best Performance with Xilinx’s DMA for PCI Express

In the case of uncorrectable ECC error, Altera recommends that you reset the core. The RX data signal can be 64 or bits. The timeout range is selectable.

Sets the read-only value of the Vendor ID register. Completion timeout error without recovery. No Application Layer intervention is required. PCI Express uses flow control. Link Training Bit The upper 12 bits of pcci memory limit register of the Type1 Configuration Space.

Altera’s FPGA PCIe chaining DMA example IP core

It can be used in production designs with caution. These settings are optimized for the parameters chosen in this reference design.

Note that the Application Layer is responsible for sending the completion with the appropriate completion status value for non-posted requests. PCI Exress uses a split-transaction for reads. Type 0 Configuration Space Header.

Maximum of 32 us.